This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits may be configured as memory circuits to store and access data. Memory circuits may be configured as arrays of memory cells (or bitcells) arranged in columns and rows. As shown in FIG. 1, a conventional memory cell array 100 may include a number of memory cells 102A, 102B, . . . , 102N in a first column 106A and a number of memory cells 104A, 104B, . . . , 104N in a second column 106B. The memory cell array 100 may be implemented in a circuit with multiple column multiplexor (colmux) passgates, such as, e.g., p-type metal-oxide-semiconductor (PMOS) transistors PA0, PA1, PB0, PB1. The memory cells 102A, 102B, . . . , 102N in the first column 106A may be selected or non-selected (i.e., activated or non-activated) when the first column mux passgates PA0, PA1 are selected or non-selected (i.e., activated or non-activated), and the memory cells 104A, 104B, . . . , 104N in the second column 106B may be selected or non-selected (i.e., activated or non-activated) when second column mux passgates PB0, PB1 are selected or non-selected (i.e., activated or non-activated).
For instance, in reference to FIG. 1, the first column 106A represents a non-selected column with use of a non-select control signal NSEL, and the second column 106B represents a selected column with use of a select control signal SEL. Further, rows of memory cells may be accessed with a number of corresponding wordlines (e.g., WLA, WLB, . . . , WLN). For instance, a first row of memory cells 102A, 104A, etc. may be accessed with a first corresponding wordline WLA, and further, a second row of memory cells 102B, 104B, etc. may be accessed with a second corresponding wordline WLB. Therefore, a particular data value may be accessed from a particular memory cell with activation of particular wordlines (e.g., WLA, WLB, . . . , WLN) corresponding to selection of particular complementary bitlines (e.g., BLA/NBLA, BLB/NBLB). In some cases, the bitlines may be implemented in a second metal layer (Metal2), and the wordlines may be implemented in a third metal layer (Metal3). Further, each of the bitlines may be coupled to a sense amplifier 108.
In conventional memory architecture, a read operation of a bitcell is triggered by activation of a wordline (e.g., WLA, WLB, . . . , WLN) connected to the bitcell's passgates (e.g., PA0/PA1, PB0/PB1). Thus, in this instance, a pull down device may start discharging the bitline. Since some bitcells share a same wordline (e.g., an entire row), the activation of the wordline may trigger the bitline discharge of all columns of bitcells coupled to this activated wordline. This is referred to as a parasitic read, since only one column may be read by activating the selected column's multiplexer and sense amplifier. In some cases, this parasitic read may translate in power inefficiency, e.g., depending on a number of columns shared by one sense amplifier, and this parasitic drop on non-active bitlines may translate to a slow wordline rising edge. Thus, in some cases, parasitic drop (together with normal, read-out drop) may cause the wordline rising to slowdown, due to the (physical existing) coupling bitline-wordline. Further, the same parasitic read may be present during a write operation because writing may involve activation of the wordline.